ISPLSI1016E-80LJ Lattice CPLD – Complex Programmable Logic Devices 5V 44-Pin PLCC

Description

Lattice Isplsi1016E-80Lj CPLD ispLSI� 1000E Family 2K Gates 64 Macro Cells 100MHz Commercial EECMOS Technology 5V 44-Pin PLCC

Specifications
Product Category: CPLD – Complex Programmable Logic Devices
Manufacturer: Lattice
RoHS: No
Product: ispLSI 1016E
Number of Macrocells: 64
Number of Logic Array Blocks – LABs: 16
Maximum Operating Frequency: 100 MHz
Propagation Delay – Max: 18.5 ns
Number of I/Os: 32 I/O
Operating Supply Voltage: 5 V
Minimum Operating Temperature: 0 C
Maximum Operating Temperature: + 70 C
Mounting Style: SMD/SMT
Package / Case: PLCC-44
Packaging: Tube
Brand: Lattice
Height: 3.68 mm
Length: 16.59 mm
Memory Type: EEPROM
Number of Gates: 2000
Operating Supply Current: 90 mA
Series: ispLSI 1016E-80L
Factory Pack Quantity: 26
Supply Voltage – Max: 5.25 V
Supply Voltage – Min: 4.75 V
Width: 16.59 mm
Unit Weight: 0.084185 oz

HIGH-DENSITY PROGRAMMABLE LOGIC
— 2000 PLD Gates
— 32 I/O Pins, Four Dedicated Inputs
— 96 Registers
— High-Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
• HIGH-PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 125 MHz Maximum Operating Frequency
— tpd = 7.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality
— Reprogram Soldered Device for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
— Lead-Free Package Options
Description
The ispLSI 1016E is a High Density Programmable Logic
Device containing 96 Registers, 32 Universal I/O pins,
four Dedicated Input pins, three Dedicated Clock Input
pins, one Global OE input pin and a Global Routing Pool
(GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 1016E offers
5V non-volatile in-system programmability of the logic, as
well as the interconnect to provide truly reconfigurable
systems. A functional superset of the ispLSI 1016
architecture, the ispLSI 1016E device adds a new global
output enable pin.
The basic unit of logic on the ispLSI 1016E device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…B7 (see Figure 1). There are a total of 16 GLBs in the
ispLSI 1016E device. Each GLB has 18 inputs, a
programmable AND/OR/Exclusive OR array, and four
outputs which can be configured to be either combinatorial
or registered. Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any other GLB on the device.

Manufacturer Part Number: ISPLSI1016E-80LJ

Manufacturer: Lattice

Datasheet: LATTS00664-1.pdf